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M6759
(1)
8-bit MTP Microcontroller
Version 1.01
Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
--Proprietary, Confidential, Preliminary--
M6759 : 8-bit MTP Micro-controller
Section 1 : Features
< 8051 instruction set compatible 8-bit microcontroller < 8051/8052 compatible pinout < Complete static design, wide range of operation frequency from 1 ~ 40 MHz < Large on-chip memory * 64K bytes built-in Multiple Times Programmable ROM (MTP-ROM) program memory * 512 bytes on-chip SRAM, expandable external 64K bytes address space < Dual Data Pointer < Four 8-bit bi-directional I/O ports < 6 interrupts including 2 external sources < One full-duplex serial UART ports compatible with standard 8052 < Three 16 bit timer/counters < On chip oscillator for crystal < Software Power-Down mode, supports Idle mode and Power Down mode for less power consumption < ROM Code Protection < 4.5V~5.5V operation voltage, 12V programming voltage < 44-pin PLCC or QFP package
1.1 General Description The M6759 is an 8032/8052 instruction compatible 8-bit microcontroller with MTP Flash ROM for firmware updating. By combining a versatile 8-bit CPU with MTP-Flash, this device provides whole microcontroller system on one chip and still remains the feasibility for general control systems in a variety of applications. Furthermore, user-defined security registers can protect the firmware after the code is ready. The M6759 contains the following: a) a non-volatile 64K bytes Multiple Times Programmable ROM program memory. b) a volatile 512 bytes read/write data memory c) four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51). d) a 16-bit timer (identical to the Timer 2 of the 8052). e) a multi-source two-priority-level nested interrupt structure. f) one serial interface (UART) and g) an on-chip oscillator.
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage : www.ali.com.tw
Page 1
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Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
Table of Contents: Section 1 : Features .............................................................................................................................................. 1 1.1 General Description..................................................................................................................................... 1 1.2 Block Diagram............................................................................................................................................. 3 Section 2 : Pin Description .................................................................................................................................... 4 Section 3 : Function Description ............................................................................................................................ 6 3.1 Data Space Addressing ............................................................................................................................... 6 3.2 Dual Data Pointer ........................................................................................................................................ 6 3.3 Low EMI Mode ............................................................................................................................................ 6 3.4 Idle Mode .................................................................................................................................................... 8 3.5 PowerDown Mode ....................................................................................................................................... 8 3.6 Reset .......................................................................................................................................................... 8 3.7 Interrupt Processing .................................................................................................................................... 8 3.8 Interrupt Masking ........................................................................................................................................ 8 3.9 Interrupt Priorities........................................................................................................................................ 9 Section 4 : Special Function Registers .................................................................................................................11 4.1 CPU Control and Status Register................................................................................................................13 4.2 Peripheral Device Registers........................................................................................................................15 Section 5 : Peripheral Device ...............................................................................................................................17 5.1 Timer Operation .........................................................................................................................................17 5.2 Serial Interface ...........................................................................................................................................20 Section 6 : Electrical Specifications ......................................................................................................................22 6.1 Absolute Maximum Ratings ........................................................................................................................22 6.2 D.C. Characteristics ...................................................................................................................................22 6.3 AC Characteristics......................................................................................................................................22 External Program Memory Read Cycle .........................................................................................................23 External Data Memory Read Cycle ...............................................................................................................23 External Data Memory Write Cycle ...............................................................................................................24 Shift Register Mode Timing Diagram ............................................................................................................25 Section 7 : Flash Programming Guide..................................................................................................................26 7.1 Description .................................................................................................................................................26 Section 8 : Packaging Information........................................................................................................................29 Worldwide Distributors and Sales Offices: ........................................................................................................31
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Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
--Proprietary, Confidential, Preliminary--
1.2 Block Diagram P0.7:0 P2.7:0 P1.7:0 P3.7:0
Port 0 Drivers
Port 2 Drivers
Port 1 Drivers Serial Port Timer Interrupt Logic
Port 3 Drivers
Port Latch
Port Latch
Port Latch
Data Bus ACC ALU REG1 Data Bus
Data Bus B Register ALU REG2 Stack Pointer ALU
Program Address Register
64K bytes MTP Memory
PSW
Program Counter Incrementer Buffer DPTR 512 Bytes RAM
Data Bus
RAM Addr. Register
Instruction Register
Clocks and Control OSC
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage : www.ali.com.tw
XTAL2 XTAL1
/EAVPP ALE /PSEN
Page 3
RST
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Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
Section 2 : Pin Description
2.1 Pinout Diagram 2.1.1 44-pin PLCC Package
T2EX T2 NC VCC AD0 AD1 AD2 AD3
7
40 1
RST RXD NC TXD /INT0 /INT1 T0 T1
M6759
18
29
AD4 AD5 AD6 AD7 /EAVPP NC ALE /PSEN A15 A14 A13
P1.5 P1.6 P1.7 RST P3.0 NC P3.1 P3.2 P3.3 P3.4 P3.5
7 1
P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3
40
M6759
18
29
P0.4 P0.5 P0.6 P0.7 /EAVPP NC ALE /PSEN P2.7 P2.6 P2.5
2.1.2 44-pin QFP Package
/WR /RD XTAL2 XTAL1 GND NC A8 A9 A10 A11 A12
T2EX T2 NC VCC AD0 AD1 AD2 AD3
1
34
RST RXD NC TXD /INT0 /INT1 T0 T1
M6759
12
23
AD4 AD5 AD6 AD7 /EAVPP NC ALE /PSEN A15 A14 A13
P1.5 P1.6 P1.7 RST P3.0 NC P3.1 P3.2 P3.3 P3.4 P3.5
1
P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3
P3.6 P3.7 XTAL2 XTAL1 GND NC P2.0 P2.1 P2.2 P2.3 P2.4
34
P0.4 P0.5 P0.6 P0.7 /EAVPP NC ALE /PSEN P2.7 P2.6 P2.5
M6759
12
23
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Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
/WR /RD XTAL2 XTAL1 GND NC A8 A9 A10 A11 A12
P3.6 P3.7 XTAL2 XTAL1 GND NC P2.0 P2.1 P2.2 P2.3 P2.4
Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
--Proprietary, Confidential, Preliminary--
2.2 Pin Description Table:
Pin assignments shown below are listed based on 44-pin PLCC package. And if not additionally specified, further pin number reference throughout this datasheet is, by default, referred to 44-pin PLCC package. As for the QFP package, the pin number assignment should be shifted accordingly, as comparatively shown in Section 2.1 Pinout Diagram.
Pin Name No. (PLCC) Type VDD 44 IN GND 22 IN P0.7-P0.0 36,37,38,39, I/O 40,41,42, 43 AD7-0 Description Power supply for internal operation, 5V input. Ground. Port 0 is 8 bits bi-directional I/O port with internal pull high. Multiplexed address/data bus. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls, the port transitions to a bidirectional data bus. This bus is used to read external ROM and read/write external RAM memory or peripherals. Reset signal of internal circuit, it must be kept 4 clocks to ensure being recognized by internal circuit. This signal will not affect internal SRAM. Crystal In, can be used as external clock input. Crystal out, feedback of XTAL1. Program Store Enable Output, commonly connected to external ROM memory as a chip enable during fetching and MOVC operation. /PSEN goes high during a reset condition. Address Latch Enable, used to latch external LSB 8 bit address bus from multiplexed address/data bus, commonly connect to the latch enable of 373 family. This signal will be forced high when the device is in a reset condition. Port 1 is 8 bits bi-directional I/O port with internal pull high. All pins have an alternate function shown as below. External timer/counter 2 trigger. External timer/counter 2. Port 2 is 8 bits bi-directional I/O port with internal pull high. The alternate function is MSB 8 bit address bus This bus emits the high-order address byte during fetches from external Program Memory or during accesses to external Data Memory that use 16-bit addresses (MOVX @ DPTR). During accesses to external Data Memory that use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function Register. Port 3 is an 8-bit bi-directional I/O port with internal pull high. The reset condition of this port is with all bits at a logic 1. Port 3 also have alternate function list below External data memory read strobe. External data memory write strobe. External timer/counter 1. External timer/counter 0. External interrupt 1 (Negative Edge Detect). External interrupt 0 (Negative Edge Detect). Serial port output. Serial port input. The pin must be externally held low to enable the device to fetch code from external program memory. If /EAVPP is held high, the device executes from internal program memory. /EAVPP is internal latched on reset. This pin also receives the 12V programming voltage (VPP) during FLASH programming. These pins should not be connected for any purpose
RST XTAL1 XTAL2 /PSEN
10 21 20 32
IN IN OUT OUT
ALE
33
OUT
9,8,7,6,5,4,3 I/O ,2 T2EX (P1.1) IN T2 (P1.0) IN P2.7-P2.0 31,30,29,28, I/O 27,26,25, 24 A15-A8 OUT
P1.7-P1.0
P3.7-P3.0
19,18,17,16, I/O 15,14,13, 11 OUT OUT IN IN IN IN OUT IN IN
/RD (P3.7) /WR (P3.6) T1 (P3.5) T0 (P3.4) /INT1 (P3.3) /INT0 (P3.2) TXD (P3.1) RXD (P3.0) /EAVPP 35
NC
1,12,23,34
NC
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage : www.ali.com.tw
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Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
Section 3 : Function Description
3.1 Data Space Addressing The M6759 has internal data memory that is mapped into four separate segments: the lower 128 bytes of RAM, upper 128 bytes of RAM, 128 bytes Special Function Register (SFR), and 256 bytes auxiliary RAM (ARAM). The four segments are: 1. The Lower 128 bytes of RAM (address 00H to 7FH) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (address 80H to FFH) are indirectly addressable only. 3. The Special Function Registers SFRs, (address 80H to FFH) are directly addressable only. 4. The 256-bytes auxiliary RAM (ARAM, 0000H-00FFH) are indirectly accessed by move external instruction, MOVX. Either direct or indirect addressing can access the lower 128 bytes. The upper 128 bytes can be accessed by indirect address only. The upper 128 bytes occupy the same address space as the SFRs. That means they have the same address, but are physically separate from SFR space. The ARAM can be accessed by indirect addressing and MOVX instructions when ARAM_EN bit is set. This part of memory is physically located on-chip, logically occupied the first 256-bytes of external data memory if ARAM_EN bit is set. The ARAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to ARAM will not affect ports P0, P3.6 (/WR) and P3.7 (/RD). If ARAM_EN is cleared, the access to external memory will be performed in the same way as standard 8051. If ARAM_EN is set and DPTR contains value lower than 0100H, the ARAM will be accessed rather than external memory, but if DPTR contains value higher than 00FFH (i.e. 0100H to FFFFH), the external memory will be accessed. If ARAM_EN is set and P2 SFR contains 00H, the ARAM will be accessed by the MOVX @Ri, #data instruction, but if P2 SFR contains a non-zero value, the external memory will be accessed using MOVX @Ri, #data. For example, MOVX DPTR, #data If ARAM_EN is set and DPTR contains 0030H, access the ARAM at address 030H rather than external memory. If ARAM_EN is set and DPTR contains 0130H, the external memory address 0130H will be accessed For example: MOVX @R0, #data If ARAM_EN is set, P2 SFR contains 00H, and R0 contains 30H, an access to the ARAM at address 30H will be performed. If ARAM_EN is set, P2 SFR contains 01H, and R0 contains 30H, an access to the external memory address 0130H will be performed if P2 is connected to the high byte address bus of external RAM. 3.2 Dual Data Pointer Data memory block moves can be accelerated using the Dual Data Pointer (DPTR). The standard 8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the M6759, the standard 16-bit data pointer is called DPTR0 and is located at SFR address 82H and 83H. These are the standard locations. The new DPTR is located at SFR 84H and 85H and is called DPTR1. The new DPTR Select bit (DPS) chooses the active pointer and is located at the LSB of the SFR location 86H. No other bits in register 86H have any effect and are set to 0. The user switches between data pointer by toggling the LSB of register 86H. The increment (INC) instruction is the fastest way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any activity. 3.3 Low EMI Mode In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purpose. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, setting bit 0 of SFR location 8EH can disable ALE operation. With the bit set, ALE is active only during a MOVX instruction. Otherwise the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the micro-controller is in external execution mode.
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Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
--Proprietary, Confidential, Preliminary--
Memory Map
Program Space
/EAVPP=0V FFFFh FFFFh
/EAVPP=5V
External ROM
Internal Flash
0000h
0000h
Data Space
ARAM_EN=1 or 0 FFFFh
External RAM
FFh
Internal RAM Upper 128 bytes
SFR space
80h 7Fh 0100h 00h 00FFh 0000h 00FFh 0000h
Lower 128 bytes
External RAM
ARAM_EN=0
Internal RAM
ARAM_EN=1
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage : www.ali.com.tw
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M6759: 8 bit MTP Micro-controller
3.4 Idle Mode In Idle mode, CPU put itself into sleep while all the on-chip peripherals remain active. The instruction that sets PCON.0 is the last instruction executed in the normal operating mode before Idle mode is activated. The content of RAM and special functions register remain unchanged, and the status of CPU (includes Stack Point, Program Counter, Program Status Word and Accumulator) is preserved in this mode. There are two ways to terminate Idle mode: * Activation of any enabled interrupt will cause IDLE (PCON.0) to be cleared by hardware terminating Idle mode. The interrupt will be serviced, and returned by instruction RETI. The next instruction to be executed is the one which follows the instruction that wrote a logic 1 to PCON.0. The flag bits GF0 (PCON.2) and GF3 (PCON.6) can be used to determine whether the interrupt was received during normal execution or during the Idle mode. When Idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. * The second way of terminating the Idle mode is with an external hardware reset.
The external reset signal is synchronous to the internal clock. The port pins will maintain high by internal pullups for 205 oscillator periods after RST pin goes low. While the RST pin is high, ALE and /PSEN are weakly pulled high. After RST is pulled low, it will take about 205 oscillator periods for ALE and PSEN to start clocking. For this reason, other devices can not be synchronized to the internal timings of the m6759. Driving the ALE and /PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state. The internal reset algorithm writes 0s to all the SFRs except the port latches, the Stack Pointer, and SBUF. The port latches are initialized to FFH, the Stack Pointer to 07H, and SBUF is indeterminate. The internal RAM is not affected by reset. On power up the RAM content is indeterminate. 3.7 Interrupt Processing When an enabled interrupt occurs, the CPU vectors to the address of the interrupt service routine (ISR) associated with that interrupt, as listed in Table 11. The CPU executes the ISR to completion unless another interrupt of higher priority occurs. Each ISR ends with a RETI (return from interrupt) instruction. After executing the RETI, the CPU returns to the next instruction that would have been executed if the interrupt had not occurred. An ISR can only be interrupted by a higher priority interrupt. That is, an ISR for a low-priority level interrupt can only be interrupted by high-priority level interrupt. An ISR for a high-priority level cannot be interrupted by any other interrupt. M6759 always completes the instruction in progress before servicing an interrupt. If the instruction in progress is RETI, or a write access to any of the IP or IE SFRs, M6759 completes one additional instruction before servicing the interrupt. 3.8 Interrupt Masking The EA bit in the IE SFR (IE.7) is a global enable for all interrupts. When EA=1, each interrupt is enabled/masked by its individual enable bit. When EA=0, all interrupts are masked.
3.5 PowerDown Mode Setting PCON.1 (PD) can force CPU enter Power Down mode. In this mode, on-chip oscillator is stopped to save most of power. All functions are stopped due to the clock frozen, but the contents of RAM and special functions register are held. To terminate Power Down mode, the only way is hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart stably. 3.6 Reset The RST is the reset input, which is the input to a Schmitt Trigger. A reset is accomplished by holding the RST pin high for at least four oscillator periods while the oscillator is running. The CPU responds by generating an internal reset, with the timing shown in Reset Timing.
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Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
--Proprietary, Confidential, Preliminary--
3.9 Interrupt Priorities There are two stages of interrupt priority assignment, interrupt level and natural priority. The interrupt level (high or low) takes precedence over natural priority. All interrupts can be assigned to be high or low priority. In addition to an assigned priority level, each interrupt also has a natural priority, as listed in Table 3-2. Simultaneous Mode Idle Idle Power Down Power Down
interrupts with the same priority level (for example, both high) are resolved according to their natural priority. For example, if /INT0 and /INT1 are both programmed as high priority, /INT0 takes precedence. Once an interrupt is being serviced, only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced.
Program Memory ALE /PSEN Port0 Port1 Port2 Internal 1 1 Data Data Data External 1 1 Float Data Address Internal 0 0 Data Data Data External 0 0 Float Data Data Table 3-1. Status of the External pins During Idle and Power Down
Port3 Data Data Data Data
Reset Timing
205 clocks State3 State4 State5 State6 State1 State2 State3 State4 State5
XTAL1 RST INTERNAL RESET SIGNAL
ALE /PSEN
P0
FF
ADDR 29 clocks
INST
ADDR
INST
STATE
STATE
STATE
STATE
STATE
STATE
STATE
STATE3 STATE4 STATE5
XTAL1 RST INTERNAL RESET SIGNAL
ALE /PSEN P0
ADDR INST ADDR FF FF
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage : www.ali.com.tw
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M6759: 8 bit MTP Micro-controller
Table 3-2. Interrupt Natural Vectors and Priorities Interrupt TF0 /INT1 TI or RI TF2 Description External interrupt 0 Timer 0 interrupt Timer 1 interrupt Serial Port transmit or receive interrupt Natural Priority 0 2 3 5 Interrupt Vector 0BH 13H 23H 2BH
Interrupt TF0 /INT1 TI or RI TF2
Description External interrupt 0 External interrupt 1 Timer 1 interrupt
Enable TCON.1 TCON.5 TCON.7 SCON0.0 SCON0.1 T2CON.7 IE.1 IE.2
Priority Control IP.0 IP.2 IP.3 IP.5
IE.6
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Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
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Section 4 : Special Function Registers
SFR Register Map Register P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 LEMI P1 AUXR SCON SBUF P2 IE P3 IP T2CON RCAP2L RCAP2H TL2 TH2 PSW ACC *P4 B *P5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Addr 80H 81H 82H 83H 84H 85H SEL 86H IDLE 87H IT0 88H M0 89H 8AH 8BH 8CH 8DH LOWEMI 8EH 90H *INT2E 97H 98H 99H A0H EX0 A8H B0H PX0 B8H CP/RL2 C8H CAH CBH CCH CDH P D0H E0H E8H F0H F8H RI Bit 0
0 SMOD TF1 GATE
0 GF4 TR1 C/T
0 GF3 TF0 M1
0 GF2 TR0 M0
0 GF1 IE1 GATE
0 GF0 IT1 C/T
0 STOP IE0 M1
0
0
0 GF5 SM2
0 *EB REN
0 *BRG1 TB8
0 *BRG0 RB8
0 *INT2I TI
ARAM_E GF6 N SM0 SM1
EA 1 TF2
*EX2 *PX2 EXF2
ET2 PT2 RCLK
ES0 PS0 TCLK
ET1 PT1 EXEN2
EX1 PX1 TR2
ET0 PT0 C/T2
CY
AC
F0
RS1
RS0
OV
F1
All registers labeled with * can be only used in 68-pin package (not available now)
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage : www.ali.com.tw
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SFR Register Initial Value Bit 7 Bit 6 P0 1 1 SP 0 0 DPL0 0 0 DPH0 0 0 DPL1 0 0 DPH1 0 0 DPS 0 0 PCON 0 0 TCON 0 0 TMOD 0 0 TL0 0 0 TL1 0 0 TH0 0 0 TH1 0 0 LEMI 0 0 P1 1 1 AUXR 0 0 SCON 0 0 SBUF 0 0 P2 1 1 IE 0 0 P3 1 1 IP 0 0 T2CON 0 0 RCAP2L 0 0 RCAP2H 0 0 TL2 0 0 TH2 0 0 PSW 0 0 ACC 0 0 P4 1 1 B 0 0 P5 1 1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1
Bit 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1
Bit 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1
Bit 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1
Bit 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1
80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 90H 97H 98H 99H A0H A8H B0H B8H C8H CAH CBH CCH CDH D0H E0H E8H F0H F8H
Page
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Register Definition
SFR 86H : DPS Register, Data Pointer Select Register Bit 7-1 0 0 SEL. The DPTR Select bit. When SEL=0, DPTR0 is the active pointer. When SEL=1, DPTR1 is the active pointer. SFR 87H : PCON Register, Power Control Register Bit Description 7 SMOD, Double Baud Rate bit. If Timer 1 is used to generate baud rate and SMOD=1, the baud rate is doubled when the Serial Port is used in modes 1, 2 or 3. 6-2 GF3- F0, General Purpose Flag bit. G 1 PD, Power Down bit. 0 IDLE, Idle Mode bit. SFR 8EH : LEMI Register, Low EMI Control Register Bit Description 7-1 0 0 LOWEMI, The Low EMI Setting bit. If the M6759 operate in the internal access mode, ALE is active only during a MOVX instruction when LOWEMI=1. SFR 97H : AUXR Register, Auxiliary Register Bit Description 7 ARAM_EN, Access Internal Auxiliary RAM Enable bit. When ARMA_EN=0, the access of external RAM will be performed by MOVX. When ARAM_EN=1, access internal auxiliary RAM rather than external RAM. 6-5 GF6-GF5. General Purpose Flag bit. 4-0 Reserved. SFR D0H : PSW Register, Program Control Register Bit Description 7 CY, Carry Flag. Set to 1 when the last arithmetic operation results in a carry into (during addition) or borrow from (during subtraction) the high order nibble. Otherwise, this bit is cleared to 0 by all arithmetic operations. 6 AC, Auxiliary Carry Flag. Set to 1 when the last arithmetic operation results in a carry into (during addition) or borrow from (during subtraction) the high order nibble. Otherwise, this bit cleared to 0 by all arithmetic operations. 5 F0, User Flag 0, user addressable. Generates purpose flag for software control. 4-3 RS1-0, Register Bank Select RS1 RS0 Bank Selected 0 0 Register Bank 0, address 00h-07h 0 1 Register Bank 1, address 08h-0Fh 1 0 Register Bank 2, address 10h-17h 1 1 Register Bank 3, address 17h-1Fh 2 OV, Overflow Flag. Set to 1 when the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). Otherwise, this bit is cleared to 0 by all arithmetic operations. 1 GF, User Flag 1, user addressable. Generator purpose flag for software control. 0 F1, Parity Flag. Set to 1 when the modulo-2 sum of the 8 bits in the accumulator is 1 (odd parity), clear to 0 on even parity.
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768Homepage : www.ali.com.tw
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Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
SFR A8H : IE Register Bit 7 EA, Global Interrupt Enable. Controls masking of all interrupts except power fail interrupt. EA=0 disable all interrupts (EA overrides individual interrupt enable bits). When EA=1, each interrupt is enabled or masked by its individual enable bit. 6 Reserved. 5 ET2, Enable External Timer 2. ET2=0 disables Timer 2 interrupt (TF2). ET2=1 enables interrupts generated by TF2 flag. 4 ES0, Enable Serial Port 0 Interrupt. ES0=0 disables Serial Port 0 interrupts (TI_0 and RI_0). ES0=1 enables interrupts generated by the TI_0 or RI_0 flag. 3 ET1, Enable External Timer 1. ET1=0 disables Timer 1 interrupt (TF1). ET1=1 enables interrupts generated by TF1 flag. 2 EX1, Enable External Interrupt 1. EX1=0 disables external interrupt 1 (/INT1). EX1=1 enables interrupts generated by /INT1. 1 ET0, Enable External Timer 0. ET0=0 disables Timer 0 interrupt (TF0). ET0=1 enables interrupts generated by TF0 flag. 0 EX0, Enable External Interrupt 0. EX0=0 disables external interrupt 0 (/INT0). EX0=1 enables interrupts generated by /INT0. SFR B8H : IP Register Bit Description 7 Reserved, read as 1. 6 Reserved. 5 PT2, Timer 2 Interrupt Priority Control. PT2=0 sets Timer 2 interrupt (TF2) to low priority. PT2=1 sets Timer 2 interrupt to high priority. 4 PS0, Serial Port 0 Interrupt Priority Control. PS0=0 sets Serial Port 0 interrupts (TI_0 and RI_0) to low priority. PS0=1 sets Serial Port 0 to high priority. 3 PT1, Timer 1 Interrupt Priority Control. PT1=0 sets Timer 1 interrupt (TF1) to low priority. PT1=1 sets Timer 1 interrupt to high priority. 2 PX1, External Interrupt 1 Priority Control. PX1=0 sets external interrupt 1 (/INT1) to low priority. PX1=1 sets external interrupt 1 to high priority. 1 PT0, Timer 0 Interrupt Priority Control. PT0=0 sets Timer 0 interrupt (TF0) to low priority. PT0=1 sets Timer 0 interrupt to high priority. 0 PX0, External Interrupt 0 Priority Control. PX0=0 sets external interrupt 0 (/INT0) to low priority. PX0=1 sets external interrupt 0 to high priority.
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4.2 Peripheral Device Registers Bit 7 6 5 4 3 Description TF1, Timer 1 Overflow Flag. Set to 1 when Time 1 count overflows and clears when the processor vectors to the interrupt service routine. TR1, Timer 1 Run Control. Set to 1 to enable counting on Timer 1. TF0, Timer 0 Overflow Flag. Set to 1 when Time 0 count overflows and clears when the processor vectors to the interrupt service routine. TR0, Timer 0 Run Control. Set to 1 to enable counting on Timer 0. IE1, Interrupt 1 Edge Detect. If external interrupt 1 is configured to be edge sensitive (IT1=1), IE1 is set by hardware when a negative edge is detected on the /INT1 and is automatically cleared when the CPU vectors to the corresponding interrupt service routine. In this case, IE1 can also be cleared by software. If external interrupt 1 is configured to be level-sensitive (IT1=0), IE1 is set when /INT1 is 0 and cleared when /INT1 is 1. In level-sensitive mode, software can not write to IE1. IT1, Interrupt 1 Type Selector, /INT1 is detected on falling edge when IT1=1; /INT1 is detected as a low level when IT1=0. IE0, Interrupt 0 Edge Detect. If external interrupt 0 is configured to be edge sensitive (IT0=1), IE0 is set by hardware when a negative edge is detected on the /INT0 and is automatically cleared when the CPU vectors to the corresponding interrupt service routine. In this case, IE0 can also be cleared by software. If external interrupt 0 is configured to be level-sensitive (IT0=0), IE0 is set when /INT0 is 0 and cleared when /INT0 is 1. In level-sensitive mode, software can not write to IE0. IT0, Interrupt 0 Type Selector, /INT0 is detected on falling edge when IT0=1; /INT0 is detected as a low level when IT0=0.
2 1
0
SFR 89H : TMOD Register Bit Description 7 GATE. Timer 1 Gate Control, when GATE=1, Timer 1 will clock when /INT1 and TR1 (TCON.6)= 1. When GATE=0, Timer 1 will clock only when TR1=1, regardless of the state of /INT1 6 C/T, Counter/Timer Selector, when C/T=0, Timer 1 is clocked by clk/12, depending on the state of T1M (CKCON.4). When C/T=1, Timer 1 is clocked by T1 pin. 5-4 M1-0, Timer 1 mode select bits M1 M0 Mode 0 0 Mode 0: 13 bit counter 0 1 Mode 1: 16 bit counter 1 0 Mode 2: 8 bit counter with auto-reload 1 1 Mode 3: off 3 GATE. Timer 0 Gate Control, when GATE=1, Timer 0 will clock when /INT0 and TR0 (TCON.4)= 1. When GATE=0, Timer 0 will clock only when TR0=1, regardless of the state of /INT0. 2 C/T, Counter/Timer Selector, when C/T=0, Timer 0 is clocked by clk/12, depending on the state of T0M (CKCON.3). When C/T=1, Timer 0 is clocked by T0 pin. 1-0 M1-0, Timer 0 mode select bits M1 M0 Mode 0 0 Mode 0: 13 bit counter 0 1 Mode 1: 16 bit counter 1 0 Mode 2: 8 bit counter with auto-reload 1 1 Mode 3: Two 8 bit counter
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M6759: 8 bit MTP Micro-controller
Bit 7
6
5
4
3
2 1
0
Description TF2, Timer 2 Overflow Flag. Hardware will set TF2 when the Timer 2 overflow from FFFFH, TF2 must be cleared to 0 by software. TF2 will only be set to 1 if RCLK and TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled. EXF2, Timer 2 External Flag. Hardware will set EXF2 when a reload or capture is caused by a high-to-low transition on the T2EX pin, and EXEN2 is set. EXF2 must be cleared to 0 by software. Writing a 1 to EXF2 forces a Timer 2 interrupt if enable. RCLK, Receive Clock Flag. Determine whether Timer 1 or Timer 2 is used for Serial Port 0 timing of receive data in serial mode 1 or 3. RCLK=1 selects Timer 2 overflow as the receive clock. RCLK=0 selects Timer 1 overflow as the receive clock. TCLK, Transmit Clock Flag. Determine whether Timer 1 or Timer 2 is used for Serial Port 0 timing of transmit data in serial mode 1 or 3. RCLK=1 selects Timer 2 overflow as the transmit clock. RCLK=0 selects Timer 1 overflow as the transmit clock. EXEN2, Timer 2 External Enable. EXEN2=1 enables capture or reload to occur as a result of high-to-low transition on T2EX, if Timer 2 is not generating baud rates for the serial port. EXEN2=0 causes Timer 2 to ignore all external events at T2EX. TR2, Timer 2 Run Control Flag. TR2=1 starts Timer 2, TR2=0 stops Timer 2. C/T2 Counter/Timer Selector. C/T2=0 selects a timer function for Timer 2. C/T2=1 selects a counter of falling transitions on the T2 pin. When used as a timer, Timer 2 run at 4 clocks per tick or 12 clocks per tick as programmed by CKCON.5, in all modes except baud rate generator mode. When used in baud rate generator mode, Timer 2 runs at 2 clocks per tick, independent of state of CKCON.5 CP/RL2, Capture/Reload Flag. When CP/RL2=1, Timer 2 captures occur on high-to-low transitions of T2EX, if EXEN2=1. When CP/RL2=0, auto-reloads occur when Timer2 overflows or when high-to-low transitions occur on T2EX, if EXEN2=1. If either RCLK or TCLK is set to 1, CP/RL2 will not function and Timer 2 will operate in auto-reload mode following each overflow.
SFR 98H : SCON Register Bit Description 7-6 SM1,SM0, Serial Port 0 Mode Select bits SM1 SM0 Mode 0 0 0 0 1 1 1 0 2 1 1 3 5 SM2, Multiprocessor Communication Enable. In modes 2 and 3, this bit enables the multiprocessor communication feature. If SM2=1 in mode 2 or 3, the RI will not be activated if the received 9th bit is 0. If SM2=1 is in mode 1, then RI will only be activated if a valid stop is received. In mode 0, SM2 establishes the baud rate: when SM2=0, the baud rate is clk/12; when SM2=1, the baud rate is clk/4. 4 REN, Receive Enable. When REN=1, reception is enabled. 3 TB8, Defined the state of the 9th data bit transmitted in modes 2 and 3. th 2 RB8, In modes 2 and 3, RB8 indicates the state of the 9 bit received. In mode 1, RB8 indicates the state of received stop bit. In mode 0, RB8 is not used. 1 TI, Transmit Interrupt Flag. Indicates that the transmit data word has been shifted out. In mode 0, TI is set th at the end of the 8 data bit. In all other modes, TI is set when the stop bit is placed on the TXD pin, TI must be cleared by software. 0 RI, Receive Interrupt Flag. Indicates that serial data word has been received. In mode 0, RI is set at the end of the 8th data bit. In mode 1, RI is set after the last sample of the incoming stop bit, subject to the state of SM2. In modes 2 and 3, RI is set at the end of the last sample of RB8, RI must be cleared by the software.
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Section 5 : Peripheral Device
The M6759 has three 16-bit timer/counter registers, all three can be configured to operate either as timers or event counters.
oscillator periods. Thus, one can view the register as a counter with count rate 1/12 of oscillator frequency. When operating as counter function, the register increases according to a 1-to-0 transition at corresponding external input
In this function, the external input pin is sampled at every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the counter increases by 1. Since it takes two machine cycles to determine a transition, the count machine cycle to ensure the given level to be sampled. In addition to the timer/counter selection, Timer 0 and Timer 1 have four operating modes, Timer 2 has three operating
Timer0/Timer1 Mode Control M1 Operating Mode 0 8 bit Timer/Counter, "THx" with "TLx" as 5 bit prescaler 0 16 bit Timer/Counter, "THx" and "TLx" are cascadent 1 8 bit auto-reload timer/counter, each time "TLx" overflows, store value in "THx" into "TLx". 1 Timer 0 : TL0 and TH0 indicate two 8-bit counters controlled by Timer 1 : off Timer2 Mode Control CP/RL2 0 0 0 X X X
TR2 1 1 16-bit auto-reload 16-bit capture Non-active
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M6759: 8 bit MTP Micro-controller
Timer/Counter Mode 0 : 13 bit Counter / 12 C/T=0 TLx 5 bit T0/T1 Pin TR1 GATE INT0/INT1 Timer/Counter Mode 2 : 8-bit Auto-Reload OSC / 12 C/T=0 C/T=1 T0/T1 Pin TR1 GATE INT0/INT1 Timer 2 in Capture Mode OSC / 12 C/T2=0 C/T2=1 T2 Pin TR2 Transition Detector T2EX Pin CONTROL EXEN2 CONTROL Timer 2 INTERRUPT RCAP2L RCAP2H 8 bit 8 bit EXF2 TL2 8 bit TH2 8 bit TF2 THx 8 bit CONTROL OVERFLOW W TL1 8 bit TFx INTERRUPT CONTROL THx 8 bit TFx INTERRUPT
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M6759: 8 bit MTP Micro-controller
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Timer 2 in Auto-reload Mode
OSC / 12 C/T2=0 C/T2=1 T2 Pin TR2 Transition Detector T2EX Pin CONTROL EXEN2 CONTROL Timer 2 INTERRUPT RCAP2L RCAP2H 8 bit 8 bit EXF2 TL2 8 bit TH2 8 bit TF2
Timer 2 In Baud Rate Generator Mode
OSC /2 C/T2=0 C/T2=1 T2 Pin TR2 Transition Detector T2EX Pin CONTROL EXEN2 EXF2 CONTROL TL2 8 bit TH2 8 bit
RCLK
Timer 1 OVERFLOW
SMOD
/2
/ 16
RX
RCAP2L RCAP2H 8 bit 8 bit Timer 2 INTERRUPT
TCLK
/ 16
TX
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M6759: 8 bit MTP Micro-controller
Timer 2 is a 16-bit Timer/Counter. It can be selected as a timer or an event counter by register T2CON. It has three operating modes: "Capture", "Auto-reload" and "Baud rate generator". In capture mode, there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 is 0, then Timer2 is a 16-bit timer/counter which sets bit TF2 (timer 2 overflow flag) upon overflowing, TF2 can generate an interrupt when Timer 2 interrupt is enabled. If EXEN2 is 1, above operation is still activated, with added feature that a 1-to0 transition of external input pin T2EX can cause the content of TL2 and TH2 to be captured into RCAP2L and RCAP2H. In addition, the transition of T2EX set the bit EXF2 (which is in the T2CON register), and EXF2 can generate an interrupt. In Auto-reload mode, there are two options that can be selected by bit EXEN2 in T2CON. If EXEN2 is 0, when Timer 2 overflows it sets TF2 and Timer 2 load the 16 bits values stored in RCAP2L and RCAP2H. If EXEN2 is 1, Timer2 still does the above, bit with an added feature that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload and set EXF2. 5.2 Serial Interface The serial port is full duplex, which means it can transmit and receive data simultaneously. There is a receive buffer to commence reception second byte before previously received byte has been read from the receive register. (If the first byte has not been completely read by the time reception of the second byte, one of the bytes will still be lost). The serial port receive and transmit data are both accessed at SBUF. Writing to SBUF loads the transmit register. Read SBUF accesses a physically separate receive register.
Baud Rates The Mode 0 Baud rate is fixed:
Mode0 Baud Rate =
Oscillator Frequency 12
Baud rate in Mode 2 depends on the bit of SMOD in Special Function Register PCON. If SMOD is 0, baud rate is 1/64 of the oscillator frequency; if SMOD is 1, baud rate is 1/32 of the oscillator frequency.
Mode2 Baud Rate =
2 SMOD x (Oscillator Frequency) 64
The Baud rate in Mode 1 and Mode 3 can be determined by overflow rate of Timer 1, Timer 2 or both (one for transmit and other for receive). When Timer 1 is used to generate Baud rate, it is determined by following equation:
Baud Rate =
2 SMOD x (Timer1 Overflow Rate) 32
The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter in any of its three running modes. In the Auto-reload mode (high nibble of TMOD = 0010B), the baud rate is given by:
Mode(1,3) Baud Rate =
2 SMOD Oscillator Frequency x 32 12 x (256 - TH 1)
When Timer 2 is used to generate Baud rate, it is set by TCLK and/or RCLK in T2CON, and the baud rate for transmit and receive can be different.
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M6759: 8 bit MTP Micro-controller
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The baud rate generator mode is similar to the auto reload mode. A rollover in TH2 cause Timer 2 to be reload with 16 bit value which stored in RCAP2H and RCAP2L.
Mode(1,3) Baud Rate =
Oscillator Frequency 32 x [65536 - (RCAP 2H , RCAP2 L )]
Mode(1,3) Baud Rate =
Timer 2 Overflow Rate 16
where (RCAP2H, RCAP2L) is the content of RCAP2H and PCAP2L taken as a 16 bit unsigned integer which is preset by software. Timer 2 in baud rate generator mode is valid only if RCLK or TCLK in T2CON is 1. The rollover in TH2 does not set TF2, and will not generate interrupt Also note that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L). In this case, T2EX can be used as an extra external interrupt if desire.
The Timer can be configured for either "timer" or "counter" operation. Normally, as a timer it increments every machine cycle (12 oscillator cycles), as a baud rate generator it increments every state time (2 oscillator cycles). In that case baud rate is give by the following formula:
Timer 1 Reload Values Common Serial Port Mode 1 Baud Rates Desired Baud SMOD C/T Timer 1 TH1 Value for 33 TH1 Value for 25 TH1 Value for Rate Mode MHz clock MHz clock 11.0592 MHz clock 57.6 Kb/s 1 0 2 FDH FEH FFH 19.2 Kb/s 1 0 2 F7H F9H FDH 9.6 Kb/s 1 0 2 EEH F2H FAH 4.8 Kb/s 1 0 2 DCH E5H F4H 2.4 Kb/s 1 0 2 B8H CAH E8H 1.2 Kb/s 1 0 2 71H 93H D0H Timer 2 Reload Values Common Serial Port Mode 1 Baud Rates 33 MHz clock 25 MHz clock Desired Baud C/T2 Rate RCAP2H RCAP2L RCAP2H RCAP2L 57.6 Kb/s 0 FFH EEH FFH F2H 19.2 Kb/s 0 FFH CAH FFH D7H 9.6 Kb/s 0 FFH 95H FFH AFH 4.8 Kb/s 0 FFH 29H FFH 5DH 2.4 Kb/s 0 FEH 52H FEH BBH 1.2 Kb/s 0 FCH A5H FDH 75H
11.0592 MHz clock RCAP2H RCAP2L FFH FAH FFH EEH FFH DCH FFH B8H FFH 70H FEH E0H
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M6759: 8 bit MTP Micro-controller
Section 6 : Electrical Specifications
6.1 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which damage to the device may occur. Continuous operation at these limits is not intended and should be limited to those conditions specified under DC electrical characteristics. Unless otherwise specified, all voltages are reference to ground. Table 6-1 Absolute Maximum Ratings Item Supply voltage Operating supply voltage (VCC) Operating supply voltage (VDD) All input and output voltages Storage temperature range (TSTG) Operating temperature (TA) 6.2 D.C. Characteristics SYMBOL VIL VIH VOL VOH ICC PARAMETERS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Supply Current (Active mode) MIN -0.5 2.4 4.0 MAX 0.8 VCC+0.5 0.5 30 Unit V V V V mA Test Conditions
Ratings -0.5V to +7V 4.5V to 5.5V 3.0V to 3.6V -0.5V to VCC+0.5V -60 oC to 150 oC 0oC to 70 oC
IOL=4.0 mA IOH= -4.0mA VDD=5V, Frequency=10MHz
6.3 AC Characteristics
SYMBOL tCLCL 1 / tCLCL tLHLL tHAVL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tRLRH tWLWH tRLDV tRHDX tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tWHLH
PARAMETERS Oscillator Clock Cycle Period Oscillator Frequency ALE Pulse Width High bytes Address Valid to ALE Low Address Valid to ALE Low Address Hold After ALE Low Address Low to Valid Instruction In ALE Low to /PSEN Low PSEN Pulse Width /PSEN Low to Valid Instruction In Input Instruction Hold After /PSEN /PSEN to Address Valid Address to Valid Instruction In /RD Pulse Width /WR Pulse Width /RD Low to Valid Data In Data Hold After /RD ALE Low to Data Valid In Address to Valid Data In ALE Low to /RD or /WR Low Address to /RD or /WR Low Data Valid to /WR Transition Data Valid to /WR High Data Hold After /WR /RD or /WR high to ALE High
MIN 25 0 2tCLCL - 40 2tCLCL - 55 tCLCL - 55 tCLCL - 35 tCLCL - 40 3tCLCL - 45 0 6tCLCL - 100 6tCLCL - 100 0 3tCLCL - 50 4tCLCL - 130 tCLCL - 60 7tCLCL - 150 tCLCL - 50 -
MAX 40 4tCLCL - 100 3tCLCL - 105 tCLCL - 25 5tCLCL - 105 5tCLCL - 165 8tCLCL - 150 9tCLCL - 165 3tCLCL + 50 tCLCL + 40
Unit ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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External Program Memory Read Cycle
tLHLL ALE
tLLPL
tPLPH tAVLL /PSEN tHAVL tLLAX PORT0 A0-A7 tAVIV PORT2 A8-A15 tPXIX INSTR IN tLLIV tPLIV
tPXAIZV
A0-A7
External Data Memory Read Cycle tLHLL ALE tWHLH /PSEN tLLWL tRLRH /RD tAVLL PORT0 tLLAX A0-A7 tAVWL tAVDV tHAVL PORT2 P2.0 - P2.7 or A8-A15 tRLDV DATA IN tRHDX A0-A7 tLLDV
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M6759: 8 bit MTP Micro-controller
External Data Memory Write Cycle
tLHLL ALE tWHLH /PSEN tLLWL tWLWH /WR tQVWX tAVLL PORT0 tLLAX A0-A7 tAVWL tRLDV tQVWH DATA OUT tWHQX
A0-A7
PORT2
P2.0 - P2.7 or A8-A15
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Serial Port Timing : Shift Register Mode Test Conditions SYMBOL PARAMETER MIN tXLXL Serial Port Clock Cycle Time 12 tCLCL tQVXH Output Data Setup to Clock Rising Edge 9tCLCL - 100 tXHQX Output Data Hold After Clock Rising Edge 3tCLCL - 100 tXHDX Input Data Hold After Clock Rising Edge 0 tXHDV Clock Rising Edge to Input Data Valid Shift Register Mode Timing Diagram
MAX 10tCLCL - 133
Unit ns ns ns ns ns
0 INSTRUCTION ALE tXLXL CLOCK tQVXH
1
2
3
4
5
6
7
8
tXHQX 0 1 2 tXHDX tXHDV 3 4 5 6 7 Set TI
WRITE TO SBUF
Output Data
CLEAR RI Input Data
Set RI
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M6759: 8 bit MTP Micro-controller
Section 7 : Flash Programming Guide
Features
* * * * * * *
64 Kbytes electrically erasable internal program memory Encrypted verifiable 3-level program memory lock 100 program/erase cycles Fully synchronous operation High performance CMOS - 100ns read access time 12v external programming voltage
7.1 Description The flash module is completely synchronous. All the operations are synchronized to the rising edge of the clock (XTAL1 pin). On the rising edge of the XTAL1, the pins' status is sampled and latched. For writing internal registers operations, the latched information is decoded during the XTAL1 high period, and execution is carried out on the falling XTAL1 edge. The flash module executes commands using an eight bit Instruction Register (IR), that defines the operation to be executed. Using the IR enables reading, programming and erasing main array and OTPR. The IR command is defined as the following table.
Table 7-1. IR Command Definition
Command Read Array Read OTPR (Key bytes or lock bits) Erase Array Erase OTPR (Key bytes or lock bits) Program Array Program OTPR (Key bytes or lock bits) Code 00h 08h 80h 88h 40h 48h
There are two modules in the flash - main array and OTPR. Main Array The module' main array contains 64K bytes of memory that serve as the code storage space for program code. The array s occupies address space from 0000H to FFFFH. OTP Rows These non-volatile cells contain 2K bytes of memory that serve as a special storage space for protection data (i.e. key bytes and lock bits).
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M6759: 8 bit MTP Micro-controller
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Note : Pin assignments shown below are listed based on 44-pin PLCC package. As for QFP package, the pin number assignment should be shifted accordingly, as comparatively shown in Section 2.1 Pinout Diagram.
Pin No. (PLCC) 44 22 35 10, 33, 18 13, 14, 32 31, 30, 29, 28, 27, 26, 25, 24 9, 8, 7, 6, 5, 4, 3, 2 36, 37, 38, 39, 40, 41, 42, 43 11 15 16 17 19 Pin Name VDD GND /EA RST, ALE, P3.6 P3.1, P3.2, /PSEN P2.7 to P2.0 P1.7 to P1.0 P0.7 to P0.0 P3.0 P3.3 P3.4 P3.5 P3.7 Signal Name Type IN IN IN IN IN IN Description Power supply for internal operation, 5V input Ground Always hold 12V during erase, programming and read flash module Always hold high during erase, programming and read flash module Always hold low during erase, programming and read flash module Input high-order address bits
Vpp High Low A15 to A8 A7 to A0 D7 to D0 /RESET IR_EN RDY /OE RD/WRb
IN Input low-order address bits IN/OUT Command/Data bus IN IN OUT IN IN Flash reset Instruction register access enable Ready signal Output enable Read/write selection The encryption function is available only when LB1 is programmed. Status Bits There are two status bits to constrain protection function in M6759. After whole chip is erased (include array and OTPR), ST0 must be programmed to 0. After key bytes and lock bits are programmed, ST1 must be programmed to 0. The status bits are in the bit1 and bit 0 of OTPR address 0004. Status bits Program Condition ST0 The bit needs to be programmed after erased. ST1 The bit needs to be programmed after protection function bytes (lock bits, key bytes) is programmed
Program Lock Bits The M6759 has 3 programmable lock bits that when programmed according to Table 7-2 will provide different levels of protection for the on-chip code and data. The lock bits are in the bit 4, bit 5 and bit 6 of OTPR address 0004. Refer to Figure 7-1 - OTPR arrangement. Table 7-2. Program Lock Bits and the Features Program Lock Bits Protection Type LB1 LB2 LB3 1 1 1 1 No Program Lock features enabled. (Code verify will be encrypted by the Encryption Array if programmed.) 2 0 1 1 MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the flash is disabled. 3 0 0 1 Same as 2, also verify is disabled. 4 0 0 0 Same as 3, also external execution is disabled. Encryption Array (key bytes) There are 4 bytes of encryption array that are initially unprogrammed (all 1' ). Every time that a byte is s addressed during verify, 2 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR' d (XNOR) with the code byte, creating an e encryption verify byte. The key bytes are in the address 0000, 0001, 0002 and 0003 of OTPR space.
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M6759: 8 bit MTP Micro-controller
0000 0001 0002 0003 0004 1
Key0 Key1 Key2 Key3
LB3 LB2 LB1 1 1 ST1 ST0
started. The RDY signal becomes low and remains low until the programming is over. During the period in which RDY signal is low, the module logic inputs are not sampled. The clock signal must be kept during RDY pin low period to ensure RDY is synchronized with the clock signal. Verify operation should be done following each byte programming. It is a read operation with built in margins performed using the IR (RD/WRb is high). If the verify fails, an additional programming cycle must be applied to the same address. Programming failure to a specific address is defined as 30 consecutive attempts to program the same address without a successful verify. Erasing This mode enables the user to erase the array and the OTPR. The cells to be erased are defined by the IR command. The command is executed upon the rising edge of the XTAL1, following writing the erase command into the IR. During erase, /OE signal must be high to avoid bus contention. The RDY signal becomes low and remains low until the erase operation is over. During the period in which RDY signal is low, the module logic inputs are not sampled. The clock signal must be kept during RDY pin low period to ensure RDY is synchronized with the clock signal. Verify procedure is a read operation with built in margins, required to confirm that all the word were successfully erased. To perform verify the user must revert the RD/WRb state to high, and apply an address to the address bus. Verify is carried out on the following rising edge of the XTAL1 signal. All addresses have to be applied sequentially in order to verify the entire array. During verify, /OE must be low to enable reading the erased cells. An erased cell has a value of ` 1' thus an ; erased byte contains FFh.
+5 V
Reserved
Figure 7-1. OTPR Arrangement Map Programming This mode enables the user to program the main memory and verify its contents. It also allows programming the OTPR. The cells to be programmed are defined by the IR command. In order to program, the required address is applied to the address bus, the required data byte is applied to the data bus and an IR program/verify instruction is executed. /OE signal must be set to high in order to avoid bus contention. This mode is operated through the Instruction Register, and requires the IR to be loaded prior to execution. Several programming pulses may be required to program a cell. Note that in order to succeed in programming, a byte must be fully erased prior to programming it. Erased byte holds the value of FFh. A written bit holds a value of zero. When programming is
Vpp High Low High /RESET Low Low IR_EN /OE High RD/WRb XTAL1 A15 - A0
/EA RST /PSEN ALE P3.0 P3.1 P3.2 P3.3 P3.5 P3.6 P3.7 XTAL1 P2.7 - P2.0, P1.7 - P1.0 GND
VDD P0.7 - P0.0 P3.4 DB7 to DB0 RDY
M6759
Fig.7-2. Flash Programming Configuration
Page 28 Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
--Proprietary, Confidential, Preliminary--
Section 8 : Packaging Information
44-pin PLCC Package
SYMBOL A B C D E F G
Dimension in Inches Min Typ 0.685 0.690 0.650 0.653 0.685 0.690 0.650 0.653 0.168 0.174 0.102 0.105 0.010
SYMBOL Max 0.695 0.656 0.695 0.656 0.180 0.108 H I J K L M
Dimension in Inches Min Typ 0.5 0.595 0.610 0.026 0.013 0.02 0.045 0.05
Max 0.625 0.032 0.021 0.04 0.055
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage : www.ali.com.tw
Page 29
--Proprietary, Confidential, Preliminary--
Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
44-pin QFP Package A
A2
0.1 0
D
A1
D1 D2
-D-
S
E1
E2
-A-
E
-B-
L C
1
ooo C A-B D bbb C A-B D
0.10 C
-C- SEATING PLANE
e
b
ccc M C A-B S D M
CONTROL DIMENSIONS ARE IN MILLIMETERS Millimeter Inch 2 Symbol Min. Nom. Max. Min. Nom. Max. R1 A 2.55 0.100 R2 A1 0.15 0.25 0.35 0.006 0.010 0.014 A2 1.90 2.05 2.20 0.075 0.081 0.087 -HCAGE D 13.20 BASIC 0.520 BASIC PLANE S 0.25mm D1 10.00 BASIC 0.394 BASIC E 13.20 BASIC 0.520 BASIC 3 L E1 10.00 BASIC 0.394 BASIC R2 0.13 0.30 0.005 0.012 R1 0.13 0.005 0 7 0 7 Symbol Millimeter Inch 1 0 0 2 10 REF 10 REF Min. Nom. Max. Min. Nom. Max. b 0.30 0.35 0.45 0.012 0.014 0.018 3 7 REF 7 REF e 0.80 BSC 0.031 BSC c 0.10 0.15 0.23 0.004 0.006 0.009 D2 8.0 0.315 L 0.73 0.88 1.03 0.029 0.035 0.041 E2 8.0 0.315 L1 1.80 0.063 ooo 0.25 0.010 c 0.10 0.15 0.23 0.004 0.006 0.009 bbb 0.20 0.008 L 0.73 0.88 1.03 0.029 0.035 0.041 ccc 0.20 0.008 L1 1.80 0.063 0.20 0.008 S NOTES : 1, DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE DIMENSIONS D1 AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE (-H-). 2, DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL. IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT. Page 30 Ver.1.01, Doc. No.: 6759DS02.doc Acer Labs: 11F, no.45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage: www.ali.com.tw
Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
--Proprietary, Confidential, Preliminary--
Worldwide Distributors and Sales Offices: Taiwan Acer Laboratories Inc. (www.ali.com.tw) 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886 (2) 8768 -2800 Fax: 886 (2) 8768 -3030 Acer Sertek 8F, no.88, Sec. 1 Hsin Tai Wu Road, HsiChih, Taipei Hsien 221,Taiwan, R.O.C. Tel: 886 (2) 2696-3232 Fax: 886 (2) 2696- 3535 Arrow / Ally, Inc. 16F, 100, Sec. 1, Hsin Tai Wu Road, HsiChih, Taipei Hsien, Taiwan, R.O.C. Tel: 886 (2) 2696 - 7388 Fax: 886 (2) 2696 - 7399 Asec International Inc. 4F, 223 Chung Yang Road, Nan Kang, Taipei, Taiwan, R.O.C. Tel: 886 (2) 2786-6677 Fax: 886 (2) 2786 - 5257 Hong Kong Lestina International Ltd. 14/F, Park Tower 15 Austin Road, Tsimshatsui, Hong Kong Tel: 852-2735 -1736 Fax: 852-2730 - 5260 Texny Glorytact (HK) Ltd. Unit M, 6/F, Kaiser Estate Phase 3, 11 Hok Yuen Street, Hunghom, Kowloon, Hong Kong Tel: 852 - 2765 - 0118 Fax: 852 - 2765 - 0557 Singapore Electronic Resources Ltd. 205 Kallang Bahru, # 04-00, Singapore 339341 Tel: 65 - 298 - 0888 Fax: 65 - 298 - 1111 Japan Unidux Inc. 11F Shin-Ohsaki Kangyo Bldg., 6-4, Ohsaki 1-Chome, Shinagawa-Ku, Tokyo, Japan 141 Tel: 81 (3) 3779 - 7828 Fax: 81 (3) 3779 - 7898 Macnica Inc. Hakusan High-Tech Park, 1-22-2 Hakusan, Midori-Ku, Yokohama City, Japan 226 Tel: 81 (45) 939 - 6106 Fax: 81 (45) 939 - 6107 Teksel Co. Ltd. 2-27-10, Higashi, Shibuya-Ku, 150-0011 Japan Tel: 81 (3) 5467-9000 Fax: 81 (3) 5467-9346 Korea I&C Microsystems Co., Ltd. 801, 8/F, Bethel Bldg., 324-1, Yangjae-Dong, Seocho-Ku, Seoul, Korea Tel: 82 (2) 577 - 9131 Fax: 82 (2) 577 - 9130 Acetronix Co. 5F Namhan Bldg., 76-42, Hannam-Dong, Yongsan-Ku, Seoul, Korea Tel. : 82 (2) 796-4561 Fax. : 82 (2) 796-4563 Italy EL.CO.MI. SRL Via Cassanese, 27 20090 Segrate - (MI), Italy Tel: 39-2-26927430 Fax: 39-2-26927410 U.S.A. ALi U. S. Office/European Operations 525 East Brokaw Road San Jose, CA 95131 USA Tel: 1 (408) 544 - 3100 Fax: 1 (408) 544 - 3135
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage : www.ali.com.tw
Page 31
--Proprietary, Confidential, Preliminary--
Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
This material is recyclable. Pentium is a trademark of Intel Corp. Windows is a trademark of Microsoft Corp. Other brands and names are the property of their respective owners. Acer Labs products are not licensed for use in medical applications, including, but not limited to, use in life support devices without proper authorization from medical officers. Buyers are requested to inform ALi sales office when planning to use the products for medical applications. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Acer Laboratories Inc. makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Acer Laboratories Inc. retains the right to make changes to these specifications at any time, without notice. Contact your local sales office to obtain the latest specifications before placing your order. ALi is a registered trademark of Acer Laboratories Incorporated and may only be used to identify ALi' s products. (c) ACER LABORATORIES INCORPORATED 1993
Page 32
Ver. 1.01, Document Number : 6759DS02.doc Acer Labs: 11F, no. 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030 Homepage : www.ali.com.tw

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